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| IN74LV245 OCTAL BUS TRANSCEIVER (3-STATE) By pinning IN74LV245 are compatible with IN74HC245A and IN74HCT245A series. Input voltage levels are compatible with standard CMOS levels. Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS Supply voltage range: 2.0 to 3.2 V Low input current: 1.0 ; 0.1 at = 25 Output current 8 m Latch current value: not less 150 m at = 125 ESD acceptable values: not less than 2000 V as per HBM and not less 200 V as per N SUFFIX PLASTIC 20 * * * * * * * 1 20 1 D SUFFIX SOIC ORDERING INFORMATION IN74LV245N Plastic DIP IN74LV245D SOIC TA = -40 to 125 C for all packages BLOCK DIAGRAM 01 DIR OE 02 03 04 05 06 07 08 09 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 18 17 16 15 14 13 12 11 19 PIN ASSIGNMENT DIR 01 A0 02 A1 03 A2 04 A3 05 A4 06 A5 07 A6 08 A7 09 GND 10 245 20 19 VCC OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7 Pin 20=VCC Pin 10 = GND FUNCTION TABLE Inputs Inputs/Output s OE DIR L L A=B input L H input B=A H X Z Z 1 IN74LV245 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Rating Unit VCC Supply voltage -0.5 to +5.0 V 1 IIK * Input diode current m 20 IOK *2 Output diode current m 50 IO *3 Output source or sink current m 35 ICC VCC current m 70 IGND GND current m 70 mW PD Power dissipation per package: 750 Plastic DIP *4 4 500 SOIC * Tstg Storage temperature range -65 to +150 C * In absolute maximum ratings modes functioning is not guaranteed. Vpon lifting the absolute maximum ratings functioning is guaranteed at the recommended operating conditions. *1 Provided VI < -0.5 V or VI > VCC + 0.5 V. *2 Provided VO < -0.5 V or VO > VCC + 0.5 V. *3 Provided -0.5 V < VO < VCC + 0.5 V. *4 When operating in the temperature range of 70 to 125C power dissipation value decreases: - for Plastic DIP by 12 mW/C - for SOIC by 8 mW/C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Supply voltage 1.2 3.6 V VIN Input voltage 0 VCC V VOUT Output voltage 0 VCC V TA Operating ambient temperature range. For all -40 125 C package types ns tLH, tHL Input rise and fall times VCC =1.2 V 0 1000 VCC =2.0 V 700 500 VCC =3.0 V 400 VCC =3.6 V 2 IN74LV245 DC CHARACTERISTICS Symbol Parameter Limits 25C -40C to 85C min max min max 0.9 VO = VCC- 1.2 0.9 1.4 0.1 V 2.0 1.4 2.1 3.0 2.1 2.5 3.6 2.5 0.3 0.3 VO =0.1 V 1.2 0.6 0.6 2.0 0.9 0.9 3.0 1.1 1.1 3.6 1.0 VI = VIH or VIL 1.2 1.1 1.9 2.0 1.92 IO = -50 2.9 3.0 2.92 3.5 3.6 3.52 VI = VIH or VIL 3.0 2.48 2.34 IO = -8 m 0.1 0.09 VI = VIH or VIL 1.2 0.1 0.09 2.0 IO = 50 0.1 0.09 3.0 0.09 0.09 3.6 VI = VIH or VIL 3.0 0.33 0.4 IO = 8 m VI = VCC or 3.6 0.1 1.0 0V 3.6 3-state 0.5 5 outputs VI = VIL or VIH VO =VCC or 0V 8.0 80 VI =VCC or 3.6 0V IO = 0 Test conditions VCC, V 125C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.09 0.5 1.0 10 Uni t V VIH HIGH level input voltage LOW level output voltage HIGH level output voltage VIL V VOH V V V VOL LOW level output voltage V II IOZ Input current OFF-state current ICC Supply current - 160 3 IN74LV245 AC CHARACTERISTICS(CL=50 pF, tLH = tHL = 6.0 ns) Limits Test VCC, Symbol Parameter condition V 25C -40C to s 85C min ma min max x 125 - 100 Propagation Figure 1 1.2 tPHL, tPLH 28 23 2.0 from An to delay 18 14 3.0 Bn, from Bn to An 140 - 120 3-state output Figure 2 1.2 tPHZ tPLZ 37 30 2.0 from OE, enable time 24 20 3.0 DIR to An, Bn 140 - 120 3-state output Figure 2 1.2 tPZH tPZL 35 28 2.0 from OE to disable time 21 17 3.0 An, Bn 75 60 1.2 tTHL, tTLH HIGH-to-LOW Figure 1 20 15 2.0 and LOW-to 13 10 3.0 HIGH transition time CI Input For inputs 3.0 7 capacitance 01,19 3.0 20 CI/ Input For capacitance inputs/ outputs 02-09, 11-18 VI = 0 V or 3.0 CPD Power 50 dissipation VCC capacitance (per one channel) 125C mi n max 140 34 21 160 43 28 160 43 26 90 24 15 - Uni t ns ns pF - - 4 IN74LV245 tLH 0.9 An, Bn 0.1 tPL H tHL 0.9 V1 V1 0.1 tPH L VCC GND 0.9 Bn, An V1 0.1 tTLH V1 = 0.5VCC 0.9 V1 tTHL 0.1 0V Figure 1 -Time diagram of AC parameters control tPLH, tPHL. tHL 0.9 OE, DIR V1 0.1 tPZ H tLH 0.9 V1 0.1 0.9 V1 tPH Z VCC GND VOH An, Bn 0V tPLZ An, Bn V1 tPZL 0.1 VOL V1 = 0.5VCC VCC Figure 2 - Time diagram of tPLZ, tPHZ, tPZL, tPZH. AC parameters control 5 IN74LV245 Drawing of the chip 2.3mm 18 19 17 16 15 14 13 12 On-chip marking 11 1.99 mm 74LV245 10 1 2 3 4 5 6 7 8 9 Pads allocation Table coordinates (counted from lower left corner), Pad mm number X Y 01 0.140 0.573 02 0.140 0.315 03 0.370 0.140 04 0.790 0.140 05 1.000 0.140 06 1.200 0.140 07 1.417 0.140 08 1.833 0.140 09 2.060 0.354 10 2.060 0.760 11 2.060 1.340 12 2.060 1.520 13 1.833 1.750 14 1.415 1.750 15 1.000 1.750 16 0.790 1.750 17 0.580 1.750 18 0.370 1.750 19 0.140 1.544 20 0.140 1.375 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 6 |
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